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this x24c01 device has been acquired by ic microsystems from xicor, inc. 1 serial e 2 prom ? xicor, 1991 patents pending characteristics subject to change without notice description the x24c01 is a cmos 1024 bit serial e 2 prom, internally organized as 128 x 8. the x24c01 feature s a serial interface and software protocol allowing ope ration on a simple two wire bus. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data retention is greater than 100 years. features ? 2.7v to 5.5v power supply ? low power cmos ? active current less than 1 ma ?standby current less than 50 a ? internally organized 128 x 8 ? 2 wire serial interface ? bidirectional data transfer protocol ? four byte page write mode ? self timed write cycle ? typical write cycle time of 5 ms ? high reliability ? endurance: 100,000 cycles ?data retention: 100 years ? 8-pin mini-dip, 8-pin msop, and 8-pin soic packages 1k x24c01 128 x 8 bit 3837 fhd f01 functional diagram start stop logic control logic h.v. generation timing & control word address counter xdec ydec d out ack e 2 prom 32 x 32 data register start cycle (8) v cc r/w pin (4) v ss (5) sda (6) scl d out load inc ck 8 3837-1.2 7/28/97 t1/c0/d0 sh ic mic ic microsystems tm
2 x24c01 nc nc nc v ss 1 2 3 4 8 7 6 5 v cc nc scl sda x24c01 plastic pin configuration pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a bidirectional pin used to transfer data in to and out of the device. it is an open drain output and m ay be wire -ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to th e guide- lines for calculating typical values of bus pull-up resistors graph. pin names symbol description nc no connect v ss ground v cc supply voltage sda serial data scl serial clock 3837 pgm t01 a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input and output timing levels v cc x 0.5 3837 pgm t02 3837 fhd f02 3837 fhd f03 equivalent a.c. load circuit 3837 fhd f16 2190 100pf output 5v dip nc nc nc v ss 1 2 3 4 8 7 6 5 v cc nc scl sda x24c01 soic/msop
x24c01 3 device operation the x24c01 supports a bidirectional bus oriented pr o- tocol. the protocol defines any device that sends d ata onto the bus as a transmitter and the receiving dev ice as the receiver. the device controlling the tran sfer is a master and the device being controlled is the slave . the master will always initiate data transfers and prov ide the clock for both transmit and receive operations. the re- fore, the x24c01 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are re- served for indicating start and stop conditions. re fer to figures 1 and 2. start condition all commands are preceded by the start condi tion, whic h is a high to low transition of sda when scl is high. the x24c01 continuously monitors the sda and scl lines for the start condition and will not resp ond to any command until this condition has been met. figure 1. data validity scl sda data stable data change 3837 fhd f06
4 x24c01 stop condition all communications must be terminated by a stop con - dition, which is a low to high transition of sda wh en scl is high. the stop condition is also used by the x24c01 to place the device in the standby powe r mode after a read sequence. a stop condition can only be issued after the transmitting device has released t he bus. acknowledge acknowledge is a software convention used to indica te successful data transfers. the transmitting device will releas e the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of d ata. refer to figure 3. the x24c01 will respond with an acknowledge after recognition of a start condition, a seven bit word address and a r/w bit. if a write operation has been select ed, the x24c01 will respond with an acknowledge after each byte of data is received. in the read mode the x24c01 will transmit eight bit s of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected an d no stop condition is generated by the master, the x24c 01 will continue to transmit data. if an acknowledge i s not detected, the x24c01 will terminate further data tr ans- missions. the master must then issue a stop conditi on to return the x24c01 to the standby power mode and place the device into a known state. figure 2. definition of start and stop 3837 fhd f07 figure 3. acknowledge response from receiver scl from master data output from transmitter 1 8 9 data output from receiver start acknowledge 3837 fhd f08 scl sda start condition stop condition
x24c01 5 write operations byte write to initiate a write operation, the master se nds a start condition followed by a seven bit word address and a write bit. the x24c01 responds with an acknowledge, then waits for eight bits of data and then responds with an acknowledge. the master then terminates the transfe r by generating a stop condition, at which time the x24c 01 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress, the x24c01 inputs are disabled, and the device will not respon d to any requests from the master. refer to figure 4 for the address, acknowledge and data transfer sequence. page write the most significant five bits of the word address define the page address. the x24c01 is capable of a four b yte page write operation. it is initiated in the same manner as the byte write operation, but instead of terminatin g the transfer of data after the first data byte, the mas ter can transmit up to three more bytes. after the receipt of each data byte, the x24c01 will respond with an acknowledge. after the receipt of each data byte, the two low or der address bits are internally incremented by one. the high order five bits of the address remain consta nt. if the master should transmit more than four data bytes pr ior to generating the stop condition, the address count er will ?roll over? and the previously transmitted data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cyc le. refer to figure 5 for the address, acknowledge and data transfer sequence. figure 4. byte write bus ac tivity: sda line bus activity: x24c01 s t a r t word address (n) s t o p p a c k data n r / w l s b s m s b a c k 3837 fhd f09 figure 5. page write bus activity: sda line bus activity: x24c01 s t a r t s s t o p p a c k a c k a c k m s b word address (n) data n data n+1 data n+3 a c k r / w l s b 3837 fhd f10
6 x24c01 figure 6. ack polling sequence acknowledge polling the disabling of the inputs can be used to take adv an tage of the typical 5 ms write cycle time. once the stop condition is issued to indicate the end of the host ?s write operation the x24c01 initiates the internal write c ycle. ack polling can be initiated immediately. this invo lves issuing the start condition followed by the word ad dress for a write operation . if the x24c01 is still busy with the write operation no ack will be returned. if the x24 c01 has completed the write operation an ack wil l be returned and the controller can then proceed with t he next read or write operation. read operations read operations are initiated in the same manner as write operations with exception that the r/w bit of the word address is set to a one. there are two basic r ead operations: byte read and sequential read. it should be noted that the ninth clock cycle of th e read operation is not a ?don?t care.? to terminat e a read operation, the master must either issue a stop cond ition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. byte read to initiate a read operation, the master sends a st art condition followed by a seven bit word address and a read bit. the x24c01 responds with an acknowledge a nd then transmits the eight bits of data. the read operation is terminated by the master; by not respo nding with an acknowl edge and by issuing a stop condition. refer to figure 7 for the start, word address, read bit, acknowledge and data transfer sequence. write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? proceed issue stop no yes yes proceed issue stop no 3837 fhd f11 figure 7. byte read 3837 fhd f12 bus activity: master sda line bus activity: x24c01 s t a r t word address n s t o p p a c k data n r / w l s b s m s b
x24c01 7 sequential rea d sequential read is initiated in the same manner as the byte read. the first data byte is transmitted as wi th the byte read mode, however, the master now resp onds with an acknowledge, indicating it requires additio nal data. the x24c01 continues to output data fo r each acknowledge received. the read operation is t ermi- nated by the master; by not responding with an ackn owl- edge and by issuing a stop condition. the data output is sequential, with the data from a ddress n followed by the data from n + 1. the address coun ter for read operations increments all address bits, al lowing the entire memory contents to be serially read duri ng one operation. at the end of the address space (add ress 127) the counter ?rolls over? to zero and the x24c0 1 continues to output data for each acknowledge re- ceived. refer to figure 8 for the address, acknowle dge and data transfer sequence. figure 8. sequential read 3837 fhd f13 figure 9. typical system configuration master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl v cc 3837 fhd f14 bus activity: sda line bus activity: x24c01 address a c k a c k data n+x s t o p p data n a c k data n+1 a c k data n+2 r / w
8 x24c01 supply voltage limits x24c01 4.5v to 5.5v x24c01-3.5 3.5v to 5.5v x24c01-3 3.0v to 5.5v x24c01-2.7 2.7v to 5.5v absolute maximum ratings* temperature under bias .................. ?65 c to +135 c storage temperature ....................... ?65 c to +150 c voltage on any pin with respect to v ss ............................ ?1.0v to +7.0v d.c. output current ............................... ............. 5 ma lead temperature (soldering, 10 seconds) ............................. 300 c *comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional ope ration of the device at these or any other conditions above t hose indicated in the operational sections of this speci fication is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c 70 c industrial ?40 c +85 c military ?55 c +125 c d.c. operating characteristics (over recommended operating conditions, unless othe rwise specified) limits symbol parameter min. max. units test conditions i cc (1) v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels i cc (2) v cc supply current (write) 2 @ 100 khz, sda = open i sb1 (1) v cc standby current 100 a scl = sda = v cc , v cc = 5v 10% i sb2 (1) v cc standby current 50 a scl = sda = v cc , v cc = 2.7v i li input leakage current 10 a v in = gnd to v cc i lo output leakage current 10 a v out = gnd to v cc v ll (2) input low voltage ?1.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1 ma 3837 pgm t03 capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v sym bol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (scl) 6 pf v in = 0v 3837 pgm t05 notes: (1) must perform a stop command prior to measurem ent. (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically s ampled and not 100% tested.
x24c01 9 a.c. characteristics (over recommended operating conditions, unless othe rwise specified) read & write cycle limits symbol parame ter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time 100 ns constant at scl, sda inputs t aa scl low to sda data out valid 0.3 3.5 s t buf time the bus must be free before a 4.7 s new transmission can start t hd:sta start condition hold time 4.0 s t low clock low period 4.7 s t high clock high period 4.0 s t su:sta start condition setup time 4.7 s t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 s t dh data out hold time 300 ns 3837 pgm t06 power - up timing symbol parameter max. units t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms 3837 pgm t07 bus timing t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 3837 fhd f04 note: (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be ini tiated. these parameters are periodically sampled and not 100% tested.
10 x24c01 write cycle limits symbol parameter min. typ. (5) max. units t wr (6) write cycle time 5 10 ms 3837 pgm t08 the write cycle time is the time from a va lid stop condition of a write sequence to the end of the int ernal erase/program cycle. during the write cycle, the x2 4c01 write cycle timing bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its word a ddress. sda 8th bit word n ack t wr stop condition start condition x24c01 address scl 3837 fhd f05 guidelines for calculating typical values of bus pull-up resistors symbol table must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance outputs inputs waveform 3837 fhd f15 120 100 80 40 60 20 20 40 60 80100120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =2.6k notes: (5) typical values are for t a = 25 c and nominal supply voltage (5v). (6) t wr is the minimum cycle time to be allowed from the s ystem perspective unless polling techniques are use d. it is the maximum time the device requires to automatically complete the internal write operation. resistance (k )
x24c01 11 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.325 (8.25) 0.300 (7.62) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.140 (3.56) 0.130 (3.30) 0.020 (0.51) 0.015 (0.38) pin 1 seating plane 0.062 (1.57) 0.058 (1.47) 0.255 (6.47) 0.245 (6.22) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 0.092 (2.34) dia. nom. half shoulder width on all end pins optional 0.015 (0.38) max. packaging information 8 - lead plastic in - line package type p note: all dimensions in inches (in parentheses in m illimeters)
12 x24c01 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.027 (0.683) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45 3926 fhd f22 8 - lead plastic small outline gull wing package type s note: all dimensions in inches (in parenthesis in m illimeters)
x24c01 13 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) ref. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ 8 - lead miniature small outlin e gull wing package type m note: 1. all dimensions in inches and (millimeters) 3003 ill 01 packaging information
14 x24c01 limited warranty devices sold by xicor, inc. are covered by the warranty and p atent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the info rmation set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of mer chantability or fitness for any purpose. xicor, inc. reserv es the right to discontinue production and change speci fications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circ uitry other than circuitry embodied in a xicor, inc. prod uct. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the followin g u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,3 14,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,7 06; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4, 874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may en da nger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor's products are not authorized for use in critical co mponents in life support devices or systems. 1. life support devices or systems are devices or systems which, ( a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance wit h instr uctions for use provided in the labeling, can be reasona bly expected to result in a significant injury to the user. 2. a critical component is any component of a life suppor t device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. device ordering information v cc limits blank = 4.5v to 5.5v 3.5 = 3.5v to 5.5v 3 = 3.0v to 5.5v 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?40 c to +85 c m = military = ?55 c to +125 c package p = 8-lead plastic dip s = 8-lead soic m = 8-lead msop x24c01 p t g - v x24c01 x g x blank = 8-lead soic p = 8-lead plastic dip m = 8-lead msop g = rohs compliant lead free blank = 4.5v to 5.5v, 0 c to +70 c f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?40 c to +85 c i = 4.5v to 5.5v, ?40 c to +85 c b = 3.5v to 5.5v, 0 c to +70 c c = 3.5v to 5.5v, ?40 c to +85 c d = 3.0v to 5.5v, 0 c to +70 c e = 3.0v to 5.5v, ?40 c to +85 c m = 4.5v to 5.5v, ?55 c to +125 c part mark convention g= rohs compliant lead free package blank = standard package. non lead free

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